1. Field of the Invention
This invention relates to electrodeposition of metals and more particularly to electrochemical metallization of substrates having surface features of different transverse dimensions.
2. Brief Description of the Prior Art
Electronic devices such as computers, cellular telephones, electronic entertainment devices, and the like, have long been manufactured by mounting components on circuit boards having electrically conductive traces thereon to interconnect the components.
In the manufacture of such electronic equipment, development of technology and economics have driven the industry toward ever-smaller devices, containing ever-increasing numbers of components. At the level of semiconductor devices very large scale integration (VLSI) and ultra large scale integration (ULSI), hereafter referred to as simply VLSI, has produced chips containing up to a few million transistors on a single semiconductor chip no larger than several millimeters on a side. Such chips have conventionally been packaged or encapsulated in small modules having external lead wires for interconnecting the chips. The interconnections have conventionally been provided by circuit boards having electrical conductors prepared by so called "printed wiring" techniques that involve masking, etching, and plating of conductive metal, usually copper, to provide the interconnects between chip modules or sockets designed to hold such modules. These "printed wiring boards" (PWB) have typically been used to interconnect chips of conventional sizes. The chips or socket are mounted on the surface of the board with terminals fitted into holes through the board. The holes are typically lined with a thin layer of copper that is integral with the traces of copper on the surface of the board. The terminals of the chips or sockets are soldered to the copper layer lining the holes and thereby interconnected through the copper traces. The PWBs may have copper traces on both sides as well as more than one inner layer of copper traces. Connections between copper traces in the different layers of these double-sided and multileyered PWBs are also provided by copper-lined holes passing through the board, commonly known as plated through-holes (PTHs).
The copper lining in such holes is typically applied electrolytically, by first laying down a thin layer of electroless copper to provide electrical continuity and then electroplating copper to a thickness of a few mils to provide the connecting layer. While the copper could be applied solely using the electroless process, the processing time for the electroless process is significantly greater than the processing time for the electrolytic process. The holes in the PWBs typically are at least 12-13 mils in diameter. Because of the well-known problem of depositing metal electrolytically in recesses, special techniques have to be used to assure that a uniform layer of conductive metal is deposited in the holes. Consequently conventional techniques to enhance the "throwing power" of the electroplating system have been employed, such as agitation of the bath, addition of certain chemical compounds to the electroplating bath, and/or the use of pulsed current plating. Furthermore, while a full-build electroless process can somewhat alleviate the throwing power issue associated with the electrolytic process, the added processing time reduces through-put.
Although conventional techniques have generally been successful in the manufacture of PWBs having the dimensions that have been commonly used in electronic devices such as television receivers, personal computers, and the like, the trend to ever-smaller equipment such as cellular telephones, palm computers, portable global positioning devices, more advanced computers, and the like, has led to the necessity of mounting chips closer together in multichip modules (MCMs). Instead of terminals extending into holes in the circuit board, such MCMs frequently have only metallized locations on a major surface of the module to provide interconnections. The semiconductor devices or chips are placed relatively close together on a substrate having holes drilled therein at the locations of the interconnecting pads on the modules. In such boards the holes are typically of smaller diameter than those of conventional PWBs, and may range from about 25 micrometers (1 mil) to about 250 micrometers (10 mils). Such holes are also effectively blind holes and the conductor deposition step provides the electrical contact to the terminal pads on the semiconductor devices as well as the interconnections between the devices. The use of small chips mounted close together and interconnected by means of conductors deposited in small holes has come to be known as high density interconnect (HDI) technology. With single sided, double sided and multilayers representing the first three generations of PWBs, high density PWBs are also being termed the fourth generation PWB. Other names for this emerging technology includes built-up boards and micro via boards. Other designs for these build up boards involves adding the chip subsequent to processing.
Furthermore, circuit boards having areas of high-density interconnections between micro via layers on either side of the PWB and conventional PWB layers or to semiconductor devices also must have structures adapted to connect the HDI board to other boards or peripheral devices. Such external connections to devices of conventional size are generally made using conventional PWB techniques, e.g., using plated-through holes. Accordingly, a single circuit board level or layer may include both areas of high-density interconnects and areas of conventional PWB connections.
As pointed out above, it has been found that the electroplating conditions suitable for fabricating plated-through holes (PTHs) are not effective to deposit metal into the smaller blind holes and vias found in the HDI areas of the board. Accordingly, the conventional procedure for manufacture of such boards has been to mask either the HDI area or the conventional PTH area of the board and plate each area under conditions appropriate for the size of the holes and recesses in the board. Typically,the full build electroless approach is utilized with the concomitant lengthy processing time and slow throughput. Further, the conditions have included special additives in the plating bath to improve the throwing power in order to promote the deposition of metal in the recesses, vias and holes. The requirement for masking certain areas of the board surface has introduced a number of processing steps, such as applying a photoresist layer, imaging the layer, developing the photoresist, and at least two separate electroplating steps, possibly in baths of different compositions.
Deposition of conductive metal into the small, blind holes or vias used in HDI has presented particular problems. Conventional metallization procedures, such as chemical vapor deposition or physical vapor deposition as well as electroless deposition, are slow and expensive. Electroplating into small blind vias using conventional procedures has not been able to provide a reliable layer of conductive metal in the vias to assure a reliable interconnection of the chips. Such a reliable layer of conductive metal may either be conforming to the via, that is conformal, or in some cases it may be desirable to fill the via. In particular, conventional electroplating techniques tend to deposit excess metal at the sharp corners at the top or entrance of the hole. Such deposits encroach on the opening of the hole and hinder deposition in the lower portion of the hole. They may even completely block the mouth of the hole leading to voids in the vias or interconnects. Furthermore, chemical additives in the plating bath may lead to inclusions of impurities derived from the plating bath within the metal deposit. Such problems can lead to connections that have a high electrical resistance and are mechanically brittle and unreliable in service. In addition, the use of nonconventional electroplating techniques such as pulse current plating, typically in conjunction with chemical additives, has relied on waveform parameters successfully developed for traditional PWB applications, such as 13 mil and greater PTHs. These waveforms generally operate with long cathodic duty cycles and short anodic duty cycles. This approach has led to similar problems encountered in conventional plating with excess metal deposit at the opening of the via leading to voids in the interconnect or to excessive deposit of metal on the surface of the substrate, a condition known to those in the industry as overplate. As well as wasting copper, overplate limits how close features may be placed an is counter to the objective of attaining higher packing densities. In addition to the problems cited above, such nonuniform metallization within the via or between the via and the substrate results in excessive processing time and cost associated with the excess metal.
Accordingly, a need has continued to exist for a method of depositing metallic conductors, especially copper, onto the surface of high-density interconnect boards with adequate deposition of metal into the small vias and recesses of the HDI areas as well as the through holes of the external connection areas.